1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a DLL (delay-locked loop) circuit for generating DLL clock signals.
2. Related Art
In general, a conventional DLL circuit is used to provide an internal clock signal the phase of which is faster by a specified time than a reference clock signal, which is obtained by converting an external clock signal. That is to say, a conventional DLL circuit is configured to make the phase of the internal clock signal faster by the specified time than the external clock signal so that output data can be output without delay with respect to the external clock signal.
Meanwhile, as the operation speed of conventional semiconductor memory apparatus increases, the ability of conventional semiconductor apparatus to output a large amount of data has also increased. In this regard, in order to output a large amount of data, a plurality of internal DLL clock signals having different phases are needed.